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fn8896 rev.2.00 page 1 of 48 nov 30, 2017 fn8896 rev.2.00 nov 30, 2017 ISL95338 bidirectional buck-boost voltage regulator datasheet the ISL95338 is a bidirectional, buck-boost voltage regulator that provides buck-boost voltage regulation and protection features. intersils advanced r3? technology is used to provide high light-load efficiency, fast transient response, and seamless dcm/ccm transitions. the ISL95338 takes input power from a wide range of dc power sources (conventional ac/dc adps, usb pd ports, travel adps, etc.) and safely conver ts it to a regulated voltage up to 24v. the ISL95338 can also convert a wide range dc pow er source connected at its output (system side) to a regul ated voltage to its input (adp side). this bidirectio nal buck-boost regulation feature makes its app lication very flexible. the ISL95338 includes various system operation functions such as forward m ode enable, reverse mode enable, programmable soft-s tart time, and adjustable v out in both the forward direction and reverse direction. the protection functionalities include ocp, ovp, uvp, otp, etc. the ISL95338 has serial communication through smbus/i 2 c that allows programming of many critical parameters to deliver a customized solution. these programming parameters include , but are not limited to: output current limit, input current limit, and output voltage setting. related literature ? for a full list of related d ocuments, visit our website ? ISL95338 product page features ? bidirectional buck, boost, and buck-boost operation ? input voltage range 3.8v to 24v (no dead zone) ? output voltage up to 20v ? up to 1mhz switching frequency ? programmable soft-start time ? ldo output for vdd and vddp ? system status alert function ? bidirectional internal discharge function ? active switching for negative voltage transitions ? bypass mode in both directions ? forward mode enable, reverse mode enable ? ocp, ovp, uvp, and otp protection ? smbus and auto-increment i 2 c compatible ? pb-free (rohs compliant) ? 32 ld 4x4 tqfn package applications ? tablet, ultrabook, power b ank, mobile devices, and usb-c
fn8896 rev.2.00 page 2 of 48 nov 30, 2017 ISL95338 figure 1. typical application circuit ISL95338 boot1 phase1 ugate1 vddp lgate1 lgate2 ugate2 phase2 boot2 scl sda csop cson dcin vdd compf frwpg rvsen adps frwen gnd csip csin addr0 v in (adapter side ) vsys (system side) prog 20m v in v out prochot # adp q1 q2 q4 q3 rs1 l1 10m rs2 vouts vout rvspg compr addr 1 ref
fn8896 rev.2.00 page 3 of 48 nov 30, 2017 ISL95338 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 simplified application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 thermal information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 recommended operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 smbus timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4. general smbus architectu re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 smbus transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 smbus and i 2 c compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5. ISL95338 smbus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 setting system side curr ent limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 setting input current limit in forward mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 setting system regulating v oltage in forward mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 setting prochot# threshold fo r adp side overc urrent conditio n . . . . . . . . . . . . . . . . . . . 25 5.5 setting prochot# threshold fo r system side overcurrent condi tion . . . . . . . . . . . . . . . . . 25 5.6 setting prochot# debounce time and duration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.8 regulating voltage register in reverse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.9 output current limit registe r in reverse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.10 input voltage limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.11 information register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6. application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1 r3 modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 ISL95338 bidirectional buck-b oost voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.4 programming options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5 de operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
fn8896 rev.2.00 page 4 of 48 nov 30, 2017 ISL95338 6.6 forward mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.7 reverse mode for usb otg (on-the-go). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.8 fast ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.9 fast swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.10 way overcurrent protectio n (wocp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.11 adp input overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.12 system output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.13 system output undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.14 adp output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.15 adp output undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 6.16 over-temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.17 switching power mosfet gate capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.18 adp side input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7. general applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 select the lc output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 select the input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3 select the switching power mosfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.4 select the bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5 select the resistor divider for vouts and adps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8. revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9. package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10. about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
fn8896 rev.2.00 page 5 of 48 nov 30, 2017 ISL95338 1. overview 1. overview 1.1 block diagram figure 2. block diagram prog scl smbus/i 2 c digital control and fuse logic dac and cntl logic for oc/ ov/uv/ ot 5v ldo buck/boost pwm modulator and driver drv 0.8v csin csip vdd sda dcin fwrpg fwren boot1 ugate1 phase1 lgate1 gnd lgate2 vddp phase2 ugate2 boot2 compr drv prochot# buf adp vref acdac acfb ifb2dac ifb2 csip vindac low pwr ldo vout cmp cmp dchotdac cmp 4.1v cmp cmp 3.8v 2.7v + - + + - + - - + + - - - - + + + + - - rev fwd cson csop 18x + - 18x + - rev fwd 18x - + 18x - + vout rev fwd compf comp drv ~1v rvspg rvsen + - addr1 addr0 fwd vdac + - 1ua rev vdac ref vouts adps fwd rev dchotdac cmp + - cmp + - ov uv -1100mv+ +fwd:820mv- +rev:1200mv cmp + - softstart pgood loop selector error amplifier
fn8896 rev.2.00 page 6 of 48 nov 30, 2017 ISL95338 1. overview 1.2 simplified application circuit figure 3. simplified application diagram 1.3 ordering information part number ( notes 3 , 4 )part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL95338hrtz ( note 1 ) 95338h -10 to +100 32 ld 4x4 tqfn l32.4x4a ISL95338irtz ( note 2 ) 95338i -40 to +100 32 ld 4x4 tqfn l32.4x4a ISL95338eval1z evaluation board notes: 1. add -t7a suffix for 250 unit,-tk suffix for 1k unit, or -t suffix for 6k unit tape and reel options. refer to tb347 for details on reel specifications. 2. add -tk suffix for 1k unit o r -t suffix for 6k unit tape and reel options. refer to tb347 for details on reel specifications. 3. these pb-free plastic packaged products employ special pb-fre e material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal ( e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). pb-free products are msl classified at p b-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), see the product informa tion page for ISL95338 . for more information on msl, refer to tb363 . ISL95338 boot1 phase1 ugate1 vddp lgate1 lgate2 ugate2 phase2 boot2 scl sda csop cson dcin vdd compf frwpg rvsen adps frwen gnd csip csin addr0 v in (adapter side) vsys (system side) prog 20m v in v out prochot# adp q1 q2 q4 q3 rs1 l1 10m rs2 vouts vout rvspg compr addr1 ref 3.3v frwpg rvspg scl sda
fn8896 rev.2.00 page 7 of 48 nov 30, 2017 ISL95338 1. overview 1.4 pin configuration ISL95338 (32 ld 4x4 tqfn) top view 1.5 pin descriptions pin number pin name description bottom pad gnd signal common of the ic. unless otherwise stated, signals ar e referenced to the gnd pin. it should also be used as the thermal pad for heat dissipation. 1csonforward v out current sense - i nput. connect to vout current resistor nega tive input. place a 0.1f ceramic capacitor between csop and cson to provide differential mode filtering. 2csopforward v out current sense + input. connect to vout current resistor posi tive input. place a 0.1f ceramic capacitor between csop and cson to provide differential mode filtering. 3 vouts forward vsys feedback voltage. use a resistor divider ext ernally to configure forward vsys voltage. 4 boot2 high-side mosfet q4 gate driver supply. connect an mlcc c apacitor across the boot2 pin and the phase2 pin. the boot capacitor i s charged through an internal b oot diode connected from the vddp pin to the boot2 pin when the phase2 pin drops below vddp minus the voltage drop across the internal boot diode. 5 ugate2 high-side mosfet q4 gate drive. 6 phase2 current return path for the high side mosfet q4 gate dri ve. connect this pin to the node consisting of the high-side mosfet q4 source, t he low-side mosfet q3 drain, a nd the one terminal of the inductor. 7 lgate2 low-side mosfet q3 gate drive. 8 vddp power supply for the gate drivers. connect to vdd pin thro ugh a 4.7 resistor and connect a 1f ceramic capacitor to gnd. 9 lgate1 low-side mosfet q2 gate drive. 10 phase1 current return path for the high side mosfet q1 gate dr ive. connect this pin to the node consisting of the high-side mosfet q1 source, the low-side mosfet q2 drain, a nd the input terminal of the inductor. 11 ugate1 high-side mosfet q1 gate drive. addr1 vout compr ref compf prog rvspg addr0 lgate1 phase1 ugate1 boot1 adps csin csip adp cson csop vouts boot2 ugate2 phase2 lgate2 vddp frwpg prochot# scl sda rvsen frwen vdd dcin 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 gnd (bottom pad)
fn8896 rev.2.00 page 8 of 48 nov 30, 2017 ISL95338 1. overview 12 boot1 high-side mosfet q1 gat e driver supply. connect an mlcc capacitor across the boot1 pin and the phase1 pin. the boot capacitor i s charged through an internal b oot diode connected from the vddp pin to the boot1 pin when the phase1 pin drops below vddp minus the voltage drop across the internal boot diode. 13 adps reverse output voltage feedback. use a resistor divider e xternally to configure the reverse output voltage. 14 csin adp current sense - input. 15 csip adp current sense + input. the modulator also uses this for sensing input voltage in forward mode and output voltage in reverse mode. 16 adp used to sense adp voltage. when adp voltage is higher than 4.1v, forward mode can be enabled. the adp pin is also one of the two internal low power ldo input s. 17 dcin input of an internal ldo providing power to the ic. conne ct a diode or from adp and system outputs. bypass this pin with an mlcc capacitor. 18 vdd output of the internal ldo; provide the bias power for the internal analog and digi tal circuit. connect a 1f ceramic capacitor to gnd. if vdd is pulled below 2.7v, the ISL95338 will reset all the sm bus register values to the default. 19 frwen forward mode enable, analog signal input. forward mode i s valid if the frwen pin voltage is greater than 0.8v. 20 rvsen reverse mode enable, digital signal input. reverse mode is valid if the signal is 1 (logic high), otherwise, reverse mode is disabled. 21 sda smbus data i/o. connect to the data line from the host con troller. connect a 10k pull-up resistor according to the smbus specification. 22 scl smbus clock i/o. connect to th e clock line from the host c ontroller. connect a 10k pull-up resistor according to the smbus specification. 23 prochot# open-drain output. pul led low when input currentis de tected as hot in forward and reverse mode. smbus command to pull low (refer to table 8 on page 25 and table 10 on page 26 for control 2 register 0x3dh and control4 register 0x4eh). 24 frwpg open-drain output. indica tor output to indicate the forw ard modulator is enabled. 25 addr0 address setting pin for the ic. the ic address is set by addr0 and addr1 logic voltage levels. 26 rvspg open-drain output. indicator output to indicate the reve rse modulator is enabled. 27 prog a resistor from prog pin to gnd sets the default forward system output voltage. 28 compf forward mode error amplifier output. connect a compensat ion network externa lly from compf to gnd. 29 ref output voltage soft-start r eference. a ceramic capacitor f rom ref to gnd is set to the desired soft-start time. in forward mode, forward output voltage (vouts) reference soft-start time is set. in reverse mode, reverse output voltage (adps) ref erence soft-start time is set. 30 compr reverse mode error am plifier output. connect a compensat ion network externally from compr to gnd. 31 vout forward v out sense voltage for modulator and phase 2 zero-current comparato r. 32 addr1 address setting pin for the ic. the ic address is set by addr0 and addr1 logic voltage levels. pin number pin name description
fn8896 rev.2.00 page 9 of 48 nov 30, 2017 ISL95338 2. specifications 2. specifications 2.1 absolute maximum ratings parameter minimum maximum unit csip, csin, dcin, adps, adp -0.3 +30 v csip 0.3 adp + 2 v phase1 gnd - 0.3 +30 v phase1 gnd - 2 (<20ns) +30 v ugate1 phase1 - 0.3 boot1 + 0.3 v phase2 gnd - 0.3 +30 v phase2 gnd - 2 (<20ns) +30 v ugate2 phase2 - 0.3 boot2 + 0.3 v lgate1, lgate2 gnd - 0.3 vddp + 0.3 v lgate1, lgate2 gnd - 2 (<20ns) vddp + 0.3 v vout, vouts, csop, cson -0.3 +27 v vdd, vddp -0.3v +6.5 v boot1, boot2 - 0.3 vddp + 27 v boot1 (phase1 - 0.3) phase1 + 6.5 v boot2 (phase2 - 0.3) phase2 + 6.5 v compr, compf, ref, prog -0.3 +6.5 v rvsen, frwen, addr0, addr1 -0.3 +6.5 v frwpg, prochot#, rvspg -0.3 +6.5 v scl, sda -0.3 +6.5 v boot1-phase1, boot2-phase2 -0.3 +0.3 v csip-csin, csop-cson 2ma esd rating rating unit human body model (tested per js-001-2014) 2 kv machine model (tested per jesd22-a115c) 200 v charged device model (tested per js-002-2014) 1 kv latch-up (tested per jesd78e) 100 ma caution: do not operate at or near the maximum ratings listed f or extended periods of time. exposure to such conditions may adversely impact product reliabi lity and result in failures not covered by warranty.
fn8896 rev.2.00 page 10 of 48 nov 30, 2017 ISL95338 2. specifications 2.2 thermal information 2.3 recommended operation conditions 2.4 electrical specifications thermal resistance (typical) ? ja (c/w) ? jc (c/w) 32 ld tqfn package ( notes 5 , 6 )37 2 notes: 5. ? ja is measured in free air with the component mounted on a high-e ffective thermal conductivity tes t board with direct attach features. see tb379 . 6. for ? jc , the case temp location is the center of the ceramic on the p ackage underside. parameter minimum maximum unit junction temperature range (t j ) -10 +125 c storage temperature range (t s ) -65 +150 c pb-free reflow profile refer to tb493 parameter minimum maximum unit ambient temperature - hrtz -10 +100 c ambient temperature - irtz -40 +100 c adp input voltage +4 +24 v v out input voltage +4 +20 v operating conditions: adp = csip = csin = 4v and 23v, vouts = v out = csop = cson = 8v, unless otherwise noted. boldface limits apply across the junction temperature range, -10c to +1 25c unless otherwise specified. parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit uvlo/acok vadp uvlo rising vadp_uvlo_r 3.9 4.2 4.55 v vadp uvlo hysteresis vadp_uvlo_h 530 mv v out uvlo rising vout_uvlo_r 3.9 4.2 4.55 v v out uvlo hysteresis vout_uvlo_h 300 mv vdda 2p7 rising, smbus active ( note 8 ) vdd_2p7_r 2.5 2.7 2.9 v vdda 2p7 por hysteresis ( note 8 ) vdd_2p7_h 150 mv vdda 3p8 por rising, modulator, and gate driver active vdd_3p8_r 3.6 3.8 3.9 v vdd 3p8 hysteresis vdd_3p8_h 150 mv frwen rising frwen_r 0.775 0.8 0.825 v frwen hysteresis frwen_h 50 mv bias current forward supply current, disable state adp, adps csin, csip, vddp, dcin = 5v, fwren = low 130 200 a reverse supply current, disable state v out , vouts cson, csop, vddp, dcin = 5v, rvsen = low 70 150 a forward supply current, enable state adp, adps csin, csip, dcin = 20v, fwren = high 3000 3300 a
fn8896 rev.2.00 page 11 of 48 nov 30, 2017 ISL95338 2. specifications reverse supply current, enable state vout, vouts cson, csop, dcin = 20v, rvsen = high 3000 3300 a forward supply current, enable state dcin only (does not include gate driver current) 1600 2000 a reverse supply current, enable state dcin only (does not include gate driver current) 1600 2000 a linear regulator vdda output voltage vdd 6v < v adp < 23v, no load 4.5 5.1 5.5 v vdda dropout voltage vdd_dp 30ma, v dcin = 4v 100 mv vdd overcurrent threshold vdd_oc 90 135 165 ma adp current regulation, r adp = 20m input current accuracy | csip - csin| = 80mv 4 a -3 +3 % |csip - csin| = 40mv 2 a -4 +4 % |csip - csin| = 10mv 0.5 a -10 +10 % adp current prochot# threshold r s1 = 20m i adp_hot_th10 acprochot = 0x0a80h (2688ma) 2688 ma -3.0 +3.0 % acprochot = 0x0400h (1024ma) 1024 ma -6.0 +6.0 % voltage regulation output voltage accuracy forward hrtz measured at vouts, 8v and up -1 +1 % output voltage accuracy forward hrtz measured at vouts, 4v to 8v -1.5 +1.5 % output voltage accuracy reverse hrtz measured at adps, 8v and up -1 +1 % output voltage accuracy reverse hrtz measured at adps, 4v to 8v -1.5 +1.5 % output voltage accuracy forward irtz measured at vouts, 8v and up -2 +2 % output voltage accuracy forward irtz measured at vouts, 4v to 8v -1.5 +1.5 % output voltage accuracy reverse irtz measured at adps, 8v and up -2 +2 % output voltage accuracy reverse irtz measured at adps, 4v to 8v -3 +3 % minimum input voltage accuracy measured at adps -3 +3 v v out current regulation, r s2 = 10m v out current accuracy |cs op - cson| = 60mv 6 a -3 +3 % |csop - cson| = 20mv 2 a -5 +5 % |csop - cson| = 10mv 1 a -10 +10 % |csop - cson| = 5mv 0.5 a -20 +20 % adp current-sense amplifier, r adp = 20m csip/csin input voltage range v csip/n 027 v operating conditions: adp = csip = csin = 4v and 23v, vouts = v out = csop = cson = 8v, unless otherwise noted. boldface limits apply across the junction temperature range, -10c to +1 25c unless otherwise specified. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit
fn8896 rev.2.00 page 12 of 48 nov 30, 2017 ISL95338 2. specifications v out current-sense amplifier, r bat = 10m system side current prochot# threshold, r s2 = 10m i sys_hot systemsideprochot = 0x1000h (4096ma) 4096 ma -5 +5 % rvsen high-level input voltage 0.9 v low-level input voltage 0.35 v input leakage current v rvsen = 3.3v, 5v 1 a prochot#, rvspg, fwrpg output sinking current pin at 0.4v 37 ma leakage current 1 a prochot# prochot# debounce time ( note 8 ) prochot# debounce register -15 15 % prochot# duration time ( note 8 ) prochot# duration register -15 15 % protection adp overvoltage rising hysteresis forward mode 25.5 26.4 27 v adp overvoltage hysteresis 0.35 v vouts overvoltage rising threshold forward mode vouts-12xref 0.85 1.1 1.45 v vouts overvoltage hysteresis 0.55 v adps overvoltage rising threshold reverse mode adps-12xref 0.9 1.2 1.5 v adps overvoltage hysteresis 0.6 v vouts undervoltage falling threshold forward mode vouts-12xref -1.15 -0.85 -0.55 v vouts undervoltage hysteresis 0.6 v adps undervoltage falling threshold reverse mode adps-12xref -1.55 -1.2 -0.85 v adps undervoltage hysteresis 0.4 v over-temperature threshold ( note 8 ) 140 150 160 c oscillator oscillator frequency, digital core only 0.85 1 1.15 mhz digital debounce time accuracy pv debounce and uv debounce for fwrpg and rvspg delay -15 15 % miscellaneous switching frequency accuracy all programmed f sw settings, ccm, and no period stretching -15 15 % adp discharge current adp = 5v 6.5 ma v out discharge current v out = 5v 8.5 ma ref pin sink/source current control1 <3> = 0 0.7 a ref pin fast sink current control1 <3> = 1 0.7 a ref pin fast source current control1 <3> = 1 14 a operating conditions: adp = csip = csin = 4v and 23v, vouts = v out = csop = cson = 8v, unless otherwise noted. boldface limits apply across the junction temperature range, -10c to +1 25c unless otherwise specified. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit
fn8896 rev.2.00 page 13 of 48 nov 30, 2017 ISL95338 2. specifications smbus sda/scl input low voltage 3.3v 0.8 v sda/scl input high voltage 3.3v 2 v sda/scl input bias current 3.3v 1 a sda, output sink current ( note 8 ) sda = 0.4v 4 ma smbus frequency f smb 10 400 khz gate driver ugate1 pull-up resistance ug1 rpu 100ma source current 800 1200 ? m ugate1 source current ug1 src ugate1 - phase1 = 2.5v 1.3 2a ugate1 pull-down resistance ug1 rpd 100ma sink current 350 475 m ugate1 sink current ug1 snk ugate1 - phase1 = 2.5v 1.9 2.8 a lgate1 pull-up resistance lg1 rpu 100ma source current 800 1200 m lgate1 source current lg1 src lgate1 - gnd = 2.5v 1.3 2a lgate1 pull-down resistance lg1 rpd 100ma sink current 300 450 m lgate1 sink current lg1 snk lgate1 - gnd = 2.5v 2.3 3.5 ? a lgate2 pull-up resistance lg2 rpu 100ma source current 800 1200 ? m lgate2 source current lg2 src lgate2 - gnd = 2.5v 1.3 2a lgate2 pull-down resistance lg2 rpd 100ma sink current 300 450 m lgate2 sink current lg2 snk lgate2 - gnd = 2.5v 2.3 3.5 a ugate2 pull-up resistance ug2 rpu 100ma source current 800 1200 m ugate2 source current ug2 src ugate2 - phase2 = 2.5v 1.3 2a ugate2 pull-down resistance ug2 rpd 100ma sink current 300 450 m ugate2 sink current ug2 snk ugate2 - phase2 = 2.5v 2.3 3.5 ? a ugate1 to lgate1 dead time t ug1lg1dead 10 20 40 ns lgate1 to ugate1 dead time t lg1ug1dead 10 20 40 ns lgate2 to ugate2 dead time t lg2ug2dead 10 20 40 ns ugate2 to lgate2 dead time t ug2lg2dead 10 20 40 ns operating conditions: adp = csip = csin = 4v and 23v, vouts = v out = csop = cson = 8v, unless otherwise noted. boldface limits apply across the junction temperature range, -10c to +1 25c unless otherwise specified. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit
fn8896 rev.2.00 page 14 of 48 nov 30, 2017 ISL95338 2. specifications 2.5 smbus timing specification figure 4. gate driver timing diagram parameters symbol test conditions min ( note 7 )typ max ( note 7 )unit smbus frequency f smb 10 400 khz bus-free time t buf 4.7 s start condition hold time from scl t hd:sta 4s start condition set-up time from scl t su:sta 4.7 s stop condition set-up time from scl t su:sto 4s sda hold time from scl t hd:dat 300 ns sda set-up time from scl t su:dat 250 ns scl low period t low 4.7 s scl high period t high 4s smbus inactivity timeout maximum charging period without an smbu s write to maxsystemvoltage or adpcurrent register 175 s notes: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established b y characterization and are not production tested. 8. compliance to datasheet limits is assured by one or more meth ods: production test, charac terization, and/or design. pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr
fn8896 rev.2.00 page 15 of 48 nov 30, 2017 ISL95338 3. typical performance curves 3. typical performance curves figure 5. forward mode soft-start, 12v adp ,20v sys figure 6. reverse mode, soft-start, 12v adp ,5v sys figure 7. v sys voltage ramps up in forward mode, buck -> buck-boost -> boost operation mode transition figure 8. adp voltage ramps up in reverse mode, buck -> buck-boost -> boost o peration mode transition figure 9. reverse mode, 5v adp to 20v adp figure 10. reverse mode, 20v adp to 5v adp
fn8896 rev.2.00 page 16 of 48 nov 30, 2017 ISL95338 3. typical performance curves figure 11. forward mode, 5v sys to 20v sys figure 12. forward mode, 20v sys to 5v sys figure 13. forward mode, output voltage loop to adp current loop transition. 5v adp , 12v sys , system load 0a to 0.65a step, adp current limit = 1.5a figure 14. forward mode, output voltage loop to adapter voltage loop transition. 6v adp , input voltage limit = 5.12v, 12v sys , system load 0a to 0.78a step, system current limit = 5a, input current limit=5a figure 15. forward mode, force buck-boost mode to boost mode. 10v adp , 12v sys figure 16. reverse mode, force buck-boost mode to boost mode. 12v adp , 10v sys
fn8896 rev.2.00 page 17 of 48 nov 30, 2017 ISL95338 3. typical performance curves figure 17. forward mode, 5v adp , 12v sys , 0-2a transient load figure 18. reverse mode, 20v adp , 12v sys , 0-2a transient load
fn8896 rev.2.00 page 18 of 48 nov 30, 2017 ISL95338 4. general smbus architecture 4. general smbus architecture figure 19. general smbus architecture 4.1 data validity the data on the sda line must be stable during the high period of the scl, unless generating a start or stop condition. the high or low state of the data line can only chan ge when the clock signal on the scl line is low. refer to figure 20 . figure 20. data validity 4.2 start and stop conditions as figure 21 shows, the start condition is a h igh to low transition of the sda line while scl is high. the stop condition is a low to high transition on the sda line while scl is high. a stop condition must be sent before each start condition. figure 21. start and stop waveforms scl control output sda control output input input state machine registers memory etc. smbus slave scl control output sda control output input input state machine registers memory etc. smbus slave scl control output sda control output input input cpu smbus master to other slave devices vdd smb scl sda sda scl data line stable data valid change of data allowed sda scl s start condition p stop condition
fn8896 rev.2.00 page 19 of 48 nov 30, 2017 ISL95338 4. general smbus architecture 4.3 acknowledge each address and data transmission uses nine clock pulses. the ninth pulse is the acknowledge bit (ack). after the start condition, the master sends seven slave address bits and an r/w bit during the next eight clock pulses. during the nine clock pulse, the device that recognizes its own addres s holds the data line low to acknowledge (refer to figure 22 ). the acknowledge bit is also us ed by both the master and the slave to acknowledge r eceipt of register addresses and data. figure 22. acknowledge on the smbus 4.4 smbus transactions all transactions start with a co ntrol byte sent from the smbus master device. the control byte begins with a start condition, followed by sev en bits of slave address (refer to table 1 on page 20 ), and the r/w bit. the r/w bit is 0 for a write or 1 fo r a read. if any slave device o n the smbus bus recogni zes its address, it will acknowledge by pulling the serial data (sda) line low for the l ast clock cycle in the control byte. if no slave exists at that address or it is not ready to communicate, the data lin e will be 1, indicating a not acknowledge condition. after the control byte is sent and the ISL95338 acknowledges it , the second byte sent b y the master must be a register address byte such as 0x1 4 for the systemcurrentlimit r egister. the register a ddress byte tells the ISL95338 which register the ma ster will write or read. see table 2 on page 20 for details of the registers. after the ISL95338 receives a register addr ess byte, it will respond with an acknowledge. 4.5 byte format every byte put on the sda line mus t be eight bits long and must be followed by an ackno wledge bit. data is transferred with the most signifi cant bit (msb) fi rst and the l east significant bit (lsb) last. the lo byte data is transferred before the hi by te data. for exam ple, when writi ng 0x41a0, 0xa0 is written first and 0x41 is written second. figure 23. smbus read and write protocol 4.6 smbus and i 2 c compatibility the ISL95338 smbus minimum input logic high voltage is 2v, so i t is compatible with i 2 c with higher than 2v pull-up power supply. the ISL95338 smbus registers ar e 16 bits, so it is compatible w ith 16 bits i 2 c or 8 bits i 2 c with auto-increment capability. the chip will not acknowledge smbus communication u nless either adp or vout is higher than 4.1v. sda scl start acknowledge from slave 12 89 msb s slave addr + w a register addr a lo byte data a hi byte data a p write to a register s slave addr + w a register addr a read from a register p s slave addr + r a lo byte data a hi byte data n p s start p stop a acknowledge n no acknowledge driven by the master p driven by the ic
fn8896 rev.2.00 page 20 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands 5. ISL95338 smbus commands the ISL95338 receives control in puts from the sm bus interface a fter power-on reset (por ). the serial interface complies with the system manageme nt bus specification, which ca n be downloaded from www.smbus.org . the ISL95338 uses the smbus read-word and write-word protocols (see figure 23 on page 19 ) to communicate with the host system. the ISL95338 is an s mbus slave device and does not initiate communication on the bus. the ISL95338 address is programmable through addr0 and addr1 voltage levels (see table 1 ) to support multiple ISL95338s sharing a common smb us. connect the addr0 a nd addr1 pins to eit her ground or vdd. bits 1 and 2 are for addr0 and addr1 pins, respectively. the 1 means the pin voltage is high, while the 0 means the pin voltage i s low. from bits 3 to 7, the value is fi xed as 10010. the address is latched at ri sing vdd 2p7 por threshold. the data (sda) and clock (scl) pi ns have schmitt-trigger inputs that can accommodate slow edges. choose pull-up resistors for sda and scl to ach ieve rise times according to th e smbus specifications. the illustration in this datasheet is based on current sensing- resistors r s1 = 20m ? and r s2 = 10m, unless otherwise specified. table 1. address table addr0 addr1 read/ write binary address hex address 0 0 1 1001,0001 0x91h 0 0 0 1001,0000 0x90h 0 1 1 1001,0101 0x95h 0 1 0 1001,0100 0x94h 1 0 1 1001,0011 0x93h 1 0 0 1001,0010 0x92h 1 1 1 1001,0111 0x97h 1 1 0 1001,0110 0x96h table 2. register summary register names register address read/ write number of bits description default systemcurrentlimit 0x14 r/w 11 [12:2]11-bit, lsb size 4ma, total ra nge 6080ma, with 10m r s1 1.5a forwardregulatingvoltage 0x15 r/w 12 [14:3]12-bit, lsb size 12mv, s ee prog table 21 on page 38 5.004v 9.000v 12.000v 16.008v 20.004v control0 0x39 r/w 16 configure various options 0x0000h information1 0x3a r 16 indica te various status 0x0000h control1 0x3c r/w 16 configure various options 0x0000h control2 0x3d r/w 16 configure various options 0x0000h forwardinputcurrent 0x3f r/w 11 [12:2]11-bit, lsb size 4ma, total r ange 6080ma, with 20m r s1 set by prog pin adpinputcurrentprochot# 0x47 r/w 6 [12:7] adp input current prochot # threshold. default 3.072a, 128ma resolution for 20m r s1 , only for forward mode. 3.072a systeminputcurrentprochot# 0x48 r/w 6 [13:8] system current towards switcher prochot# threshold. default 4.096a, 256ma resolution for 10m r s2 . 4.096a
fn8896 rev.2.00 page 21 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands 5.1 setting system s ide current limit to set the system side current l imit, which is the output curre nt in forward mode or the input current in reverse mode, write a 16-bit systemcurrentlimit command (0x14h or 0b000 10100) using the write-word protocol shown in figure 5 on page 15 and the data format shown in table 3 for a 10m rs2 or table 4 for a 5m rs2. the ISL95338 limits the system current by limiting the csop-cso n voltage. by using the recommended current- sense resistor value rs2 = 10m, the registers lsb always tran slates to 4ma of out put current. the systemcurrentlimit register accepts any output current command but only the valid register bits will be written to the register and the maximum value is clamped at 6080ma for rs2 = 10m. after por, the systemcurrentlimi t register is reset to 0x05dch (1.5a). the systemcurren tlimit register can be read back to verify its content. reverseregulatingvoltage 0x49 r/w 12 [14:3] 12-bit, lsb size 12mv reverse mode regulating voltage reference 5.004v reverseoutputcurrent 0x4a r/w 6 [12:7] 6-bit, lsb size 128ma, total range 4.096a reverse mode maximum current limit 0.512a inputvoltagelimit 0x4b r/w 6 [13:8] 6-bit, lsb size 512mv forward low v in loop voltage reference 4.096v control3 0x4c r/w 16 configure various options 0x0000h information2 0x4d r 16 indica te various status 0x0000h control4 0x4e r/w 8 [7:0] 8-bit, configure various options 0x00h manufacturerid 0xfe r 8 manufacturers id register 0x49h deviceid 0xff r 8 device id register - 0x0d 0x0dh table 3. systemcurrentlimit register 0x14h (11-bit, 4ma step, 10m sense resistor, x36) bit description <1:0> not used <2> 0 = add 0ma of system current limit. 1 = add 4ma of system current limit. <3> 0 = add 0ma of system current limit. 1 = add 8ma of system current limit. <4> 0 = add 0ma of system current limit. 1 = add 16ma of system current limit. <5> 0 = add 0ma of system current limit. 1 = add 32ma of system current limit. <6> 0 = add 0ma of system current limit. 1 = add 64ma of system current limit. <7> 0 = add 0ma of system current limit. 1 = add 128ma of system current limit. <8> 0 = add 0ma of system current limit. 1 = add 256ma of system current limit. <9> 0 = add 0ma of system current limit. 1 = add 512ma of system current limit. <10> 0 = add 0ma of system current limit. 1 = add 1024ma of system current limit. <11> 0 = add 0ma of system current limit. 1 = add 2048ma of system current limit. table 2. register summary (continued) register names register address read/ write number of bits description default
fn8896 rev.2.00 page 22 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands 5.2 setting input current limit in forward mode to set the input current limit i n forward mode, write a 16-bit forwardinputcurrent command (0x3fh or 0b00111111) using the write-word protocol shown in figure 5 on page 15 and the data format shown in table 5 for a 20m rs1 or table 6 on page 23 for a 10m rs1. the ISL95338 limits the input cu rrent in forward mode by limiti ng the csip-csin voltage. by using the recommended current-sense resist or values, the registers lsb a lways translates to 4ma of input current. any input current li mit command will be accepte d but only the valid register bits will be written to the forwardinputcurrent register and the maximum val ues are clamped at 6080ma for rs1 = 20m. <12> 0 = add 0ma of system current limit. 1 = add 4096ma of system current limit. <13:15> not used maximum <12:2> = 10111110000 6080ma note: the gain for the system s ide current-sensi ng amplifiers i s different for forward mode and reverse mode. the gain in reve rse mode is half of that in forward mode. therefore, in reverse mod e, the sensing current value needs to be doubled compared to th e value set in the systemcurrentlimit register. table 4. forwardoutputcurrentlimit register 0x14h (11-bit, 8ma st ep, 5m sense resistor, x36) bit description <1:0> not used <2> 0 = add 0ma of system current limit. 1 = add 8ma of system current limit. <3> 0 = add 0ma of system current limit. 1 = add 16ma of system current limit. <4> 0 = add 0ma of system current limit. 1 = add 32ma of system current limit. <5> 0 = add 0ma of system current limit. 1 = add 64ma of system current limit. <6> 0 = add 0ma of system current limit. 1 = add 128ma of system current limit. <7> 0 = add 0ma of system current limit. 1 = add 256ma of system current limit. <8> 0 = add 0ma of system current limit. 1 = add 512ma of system current limit. <9> 0 = add 0ma of system current limit. 1 = add 1024ma of system current limit. <10> 0 = add 0ma of system current limit. 1 = add 2048ma of system current limit. <11> 0 = add 0ma of system current limit. 1 = add 4096ma of system current limit. <12> 0 = add 0ma of system current limit. 1 = add 8192ma of system current limit. <13:15> not used maximum <12:2> = 10111110000 12160ma table 3. systemcurrentlimit register 0x14h (11-bit, 4ma step, 10m sense resistor, x36) (continued) bit description
fn8896 rev.2.00 page 23 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands . table 5. forwardinputcurrent register 0x3fh (11-bit, 4ma step, 20m sense resistor, x18) bit description <1:0> not used <2> 0 = add 0ma of input current limit in forward mode. 1 = add 4ma of input current limit in forward mode. <3> 0 = add 0ma of input current limit in forward mode. 1 = add 8ma of input current limit in forward mode. <4> 0 = add 0ma of input current limit in forward mode. 1 = add 16ma of input current limit in forward mode. <5> 0 = add 0ma of input current limit in forward mode. 1 = add 32ma of input current limit in forward mode. <6> 0 = add 0ma of input current limit in forward mode. 1 = add 64ma of input current limit in forward mode. <7> 0 = add 0ma of input current limit in forward mode. 1 = add 128ma of input current limit in forward mode. <8> 0 = add 0ma of input current limit in forward mode. 1 = add 256ma of input current limit in forward mode. <9> 0 = add 0ma of input current limit in forward mode. 1 = add 512ma of input current limit in forward mode. <10> 0 = add 0ma of input current limit in forward mode. 1 = add 1024ma of input current limit in forward mode. <11> 0 = add 0ma of input current limit in forward mode. 1 = add 2048ma of input current limit in forward mode. <12> 0 = add 0ma of input current limit in forward mode. 1 = add 4096ma of input current limit in forward mode. <13:15> not used maximum <12:4> = 10111110000 6080ma. table 6. forwardinputcurrent register 0x3fh (11-bit, 8ma step, 10 m sense resistor, x18) bit description <1:0> not used <2> 0 = add 0ma of input current limit in forward mode. 1 = add 8ma of input current limit in forward mode. <3> 0 = add 0ma of input current limit in forward mode. 1 = add 16ma of input current limit in forward mode. <4> 0 = add 0ma of input current limit in forward mode. 1 = add 32ma of input current limit in forward mode. <5> 0 = add 0ma of input current limit in forward mode. 1 = add 64ma of input current limit in forward mode. <6> 0 = add 0ma of input current limit in forward mode. 1 = add 128ma of input current limit in forward mode. <7> 0 = add 0ma of input current limit in forward mode. 1 = add 256ma of input current limit in forward mode. <8> 0 = add 0ma of input current limit in forward mode. 1 = add 512ma of input current limit in forward mode. <9> 0 = add 0ma of input current limit in forward mode. 1 = add 1024ma of input current limit in forward mode. <10> 0 = add 0ma of input current limit in forward mode. 1 = add 2048ma of input current limit in forward mode.
fn8896 rev.2.00 page 24 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands 5.3 setting system regulati ng voltage in forward mode to set the regulating voltage in forward mode, write a 16-bit f orwardregulatingvoltage command (0x15h or 0b00010101) using the write-word protocol shown in figure 5 on page 15 and the data form at as shown in table 7 . the output regulating voltage range in forward mode is 2v to 24 v. the forwardregulatingvoltage register accepts any voltage command, but only the valid register bits will be w ritten to the register. the maximum value is clamped at 24.576v. the ISL95338 accepts a 0 v command, but the register value does not change. the vouts pin is the output voltage regulation sense point in forward mode. in forward mode, the customer al so can configure the regulating output voltage by setting the external voltage divider on the vouts pin without changing the forwardregulating voltage register value. <11> 0 = add 0ma of input current limit in forward mode. 1 = add 4096ma of input current limit in forward mode. <12> 0 = add 0ma of input current limit in forward mode. 1 = add 8192ma of input current limit in forward mode. <13:15> not used maximum <12:4> = 10111110000 12160ma table 7. forwardregulatingvoltage register 0x15h (12mv step) bit description <2:0> not used <3> 0 = add 0mv of regulating voltage in forward mode. 1 = add 12mv of regulating voltage in forward mode. <4> 0 = add 0mv of regulating voltage in forward mode. 1 = add 24mv of regulating voltage in forward mode. <5> 0 = add 0mv of regulating voltage in forward mode. 1 = add 48mv of regulating voltage in forward mode. <6> 0 = add 0mv of regulating voltage in forward mode. 1 = add 96mv of regulating voltage in forward mode. <7> 0 = add 0mv of regulating voltage in forward mode. 1 = add 192mv of regulating voltage in forward mode. <8> 0 = add 0mv of regulating voltage in forward mode. 1 = add 384mv of regulating voltage in forward mode. <9> 0 = add 0mv of regulating voltage in forward mode. 1 = add 768mv of regulating voltage in forward mode. <10> 0 = add 0mv of regulating voltage in forward mode. 1 = add 1536mv of regulating voltage in forward mode. <11> 0 = add 0mv of regulating voltage in forward mode. 1 = add 3072mv of regulating voltage in forward mode. <12> 0 = add 0mv of regulating voltage in forward mode. 1 = add 6144mv of regulating voltage in forward mode. <13> 0 = add 0mv of regulating voltage in forward mode. 1 = add 12288mv of regulating voltage in forward mode. <14> 0 = add 0mv of regulating voltage in forward mode. 1 = add 24576mv of regulating voltage in forward mode. <15> not used maximum 24576mv note: the default reading value of this register is 6.288v when the chip is powering up without writing any values because of the dac initial value. thus, write the needed value in this registe r before enabling forward output voltage. table 6. forwardinputcurrent register 0x3fh (11-bit, 8ma step, 10 m sense resistor, x18) (continued) bit description
fn8896 rev.2.00 page 25 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands 5.4 setting prochot# threshold for adp side overcurrent conditio n to set the prochot# assertion th reshold for adp side input over current condition in forward mode, write a 16-bit adpsideprochot# command (0x47h or 0b01000111) using the write-word protocol shown in table 5 on page 23 and the data format shown in table 8 . by using the recommended curren t-sense resistor values, the registers lsb always translates to 128ma of input current. the adpsideprochot# regist er accepts any current command, but only the valid register bits will be written to th e register. the maximum values are clamped at 6400ma for rs1 = 20m. after por, the adpsideprochot# r egister is reset to 0x0c00h. th e adpsideprochot# regist er can be read back to verify its content. if the input current exceeds the adpsideprochot# register setti ng, prochot# signal will assert after the debounce time programmed by the control2 register bit<10:9> and latch on for a minimum time programmed by control2 register bit<8:6>. 5.5 setting prochot# thr eshold for system sid e overcurrent condi tion to set the prochot# signal assert ion threshold for system side input overcurrent condition in reverse mode, write a 16-bit systemsideprochot# command (0x48h or 0b01001000) using the write-word protocol shown in table 5 on page 23 and the data format shown in table 9 . by using the recommended current-sense resistor values, the registers lsb always transl ates to 256ma of system side cu rrent. the systemsideprochot# register accepts any current command, but only the valid register bits will be writt en to the register. the max imum values are clamped at 12.8a for rs2 = 10m. after por, the systemsideprochot # register is reset to 0x1000h. the systemsideprochot# register can be read back to verify its content. if the system side current exceed s the systemsideprochot# regis ter setting, the prochot# signal will assert after the debounce time programmed by the control2 register bit<10:9> and latch on for a minimum time programmed by control2 register bit<8:6>. table 8. adpsideprochot# register 0x47h (20m sensing resistor, 1 28ma step, x18 gain) bit description <6:0> not used <7> 0 = add 0ma of adpsideprochot# threshold. 1 = add 128ma of adpsideprochot# threshold. <8> 0 = add 0ma of adpsideprochot# threshold. 1 = add 256ma of adpsideprochot# threshold. <9> 0 = add 0ma of adpsideprochot# threshold. 1 = add 512ma of adpsideprochot# threshold. <10> 0 = add 0ma of adpsideprochot# threshold. 1 = add 1024ma of adpsideprochot# threshold. <11> 0 = add 0ma of adpsideprochot# threshold. 1 = add 2048ma of adpsideprochot# threshold. <12> 0 = add 0ma of adpsideprochot# threshold. 1 = add 4096ma of adpsideprochot# threshold. <15:13> not used maximum <12:7> = 110010, 6400ma
fn8896 rev.2.00 page 26 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands 5.6 setting prochot# deboun ce time and duration time control2 register bit<10:9> conf igures the prochot# signal debo unce time before it s assertion for adpsideprochot# and systemsideprochot#. control2 register bit<8:6> configures the minimum duration of p rochot# signal once asserted. 5.7 control registers control0, control1, control2, cont rol3, and control4 registers configure the operation of the ISL95338. to change certain functions or options after por, write a 16-bit control command to control0 register (0x39h or 0b00111001), and a 16-bit control command to control1 register (0x3ch or 0b0 0111100), control2 register (0x3dh or 0b00111101), control3 register (0x4ch or 0b00111100), or contro l4 register (0x4eh or 0b00111101) using the write-word protocol shown in figure 5 and the data format shown in tables 10 , 11 , 12 , 13 , and 14 , respectively. table 9. systemsideprochot# regist er 0x48h (10m sensing resistor , 256ma step, x18 gain) bit description <7:0> not used <8> 0 = add 0ma of systemsideprochot# threshold. 1 = add 256ma of systemsideprochot# threshold. <9> 0 = add 0ma of systemsideprochot# threshold. 1 = add 512ma of systemsideprochot# threshold. <10> 0 = add 0ma of systems ideprochot# threshold. 1 = add 1024ma of systemsideprochot# threshold. <11> 0 = add 0ma of systemsideprochot# threshold. 1 = add 2048ma of systemsideprochot# threshold. <12> 0 = add 0ma of systems ideprochot# threshold. 1 = add 4096ma of systemsideprochot# threshold. <13> 0 = add 0ma of systems ideprochot# threshold. 1 = add 8192ma of systemsideprochot# threshold. <15:14> not used maximum <13:8> = 110010, 12800ma table 10. control0 register 0x39h bit bit name description <15:13> forward buck and buck-boost phase comparator threshold offset bit<15:13> adjusts phase comparator threshold offset for forwar d buck and buck-boost 000 = 0mv 001 = 1mv 010 = 2mv 011 = 3mv 100 = -4mv 101 = -3mv 110 = -2mv 111 = -1mv <12:10> forward and reverse boost phase comparator threshold offset bit<12:10> adjusts phase comparator threshold offset for forwar d and reverse boost 000 = 0mv 001 = 0.5mv 010 = 1mv 011 = 1.5mv 100 = -2mv 101 = -1.5mv 110 = -1mv 111 = -0.5mv
fn8896 rev.2.00 page 27 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands <9:7> reverse buck and buck-boost phase comparator threshold offset bit<9:7> adjusts phase comparat or threshold offset for reverse buck and buck-boost 000 = 0mv 001 = 1mv 010 = 2mv 011 = 3mv 100 = -4mv 101 = -3mv 110 = -2mv 111 = -1mv <6:5> high-side fet short detection threshold bit<6:5> configures the high-side fet short detection phase nod e voltage threshold during low-side fet turning on. 00 = 400mv (default) 01 = 500mv 10 = 600mv 11 = 800mv <4:3> not used <2> disable input voltage regulation loop bit<2> disables or enables the i nput voltage regulation loop. 0 = enable input voltage regulation loop (default) 1 = disable input voltage regulation loop <1> adp side discharge bit<1> ena ble or disable adp side charger function 0 = disable (default) 1 = enable <0> system side discharge bit<0> enable or disable system side ch arger function 0 = disable (default) 1 = enable table 11. control1 register 0x3ch bit bit name description <15> disable diode- emulation comparator bit<15> enables or disables d iode-emulation comparator. 0 = diode-emulation comparator enabled (default) 1 = diode-emulation comparator disabled <14> allow sinking current during negative dac transition bit<14> enables or disables sin king current during negative dac transition. 0 = sinking current during negat ive dac transition enabled (def ault) 1 = sinking current during negat ive dac transition disabled <13> skip trim during restart bit <13> enables or disables trim re ad during restart. make sure to program this bit when pgood is high. 0 = read trim during restart 1 = skip trim during restart <12> skip autozero during restart bit<12> enables or disables autoz ero during restart. make sure to program this bit when pgood is high. 0 = autozero during restart 1 = skip autozero during restart <11> reverse mode function bit<11> enables or disables force reve rse mode function. 0 = disable force reverse mode function (default) 1 = enable force reverse mode function <10> audio filter bit<10> enables o r disables the audio filter fu nction. no audio filter function in buck-boost mode. 0 = disable (default) 1 = enable table 10. control0 register 0x39h bit bit name description
fn8896 rev.2.00 page 28 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands <9:7> switching frequency bit<9:7> configures the switching frequ ency. 000 = 1000khz 001 = 910khz 010 = 850khz 011 = 787khz 100 = 744khz 101 = 695khz 110 = 660khz 111 = 620khz <6> not used <5> disable system side current-amp when in fwd mode without adp bit<5> enables or disables the s ystem side current amplifier wh en in fwd mode without adp. 0 = enable system side current amplifier (default) 1 = disable system side current amplifier <4> bypass mode bit<4> enables or disables the bypass mode. 0 = disable (default) 1 = enable <3> fast ref mode bit<3> enables or disables the fast ref mode. 0 = disable (default) 1 = enable <2> stop switching in fwd mode bit<2> enables or disables the buck-boost switching v out output. when disabled, ISL95338 stops switching and ref drops to ov. only valid in forward mode . 0 = enable switching (default) 1 = disable switching <1> ov enable or disable during slew-down bit<1> enable or disable ov fault when vdac slew rate down in f orward and reverse mode. 0 = enable ov (default) 1 = disable ov <0> force 5.04v vdac bit<0> enable or disable force 5.04vdac in f orward and reverse mode. 0 = disable force 5.04v vdac (default) 1 = enable force 5.04v vdac table 12. control2 register 0x3dh bit bit name description <15> ov control ov enable or disable 0 = enable ov (default) 1 = disable ov <14> uv control bit<14> enable or disable uv 0 = enable uv (default) 1 = disable uv <13> fault restart debounce for reverse enable bit<13> configures fault resta rt debounce for reverse enable. 0 = debounce time is 1.3s (default) 1 = debounce time is 150ms <12> fault restart debounce bit<13> configures fast fault restar t debounce. 0 = debounce time is 1.3s or 150m s, depends on bit<13> setting (default) 1 = debounce time is 200us or 10us, depends on bit<13> setting <11> forward restart debounce for forward enable bit<13> configures fault resta rt debounce for forward enable. 0 = debounce time is 1.3s (default) 1 = debounce time is 150ms <10:9> prochot# debounce bit<10:9> configures the prochot# deboun ce time before its assertion for adpsideprochot# and systemsideprochot#. 00: 7s (default) 01: 100s 10: 500s 11: 1ms table 11. control1 register 0x3ch (continued) bit bit name description
fn8896 rev.2.00 page 29 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands <8:6> prochot# duration bit<8:6> configures the minimum duration of prochot# signal once asserted. 000 = 10ms (default) 001 = 20ms 010 = 15ms 011 = 5ms 100 = 1ms 101 = 500s 110 = 100s 111 = 0s <5> not used <4> reverse fast swap bit<4> c onfigures reverse fast swap. 0 = disable reverse fast swap (default) 1 = enable reverse fast swap <3> forward fast swap bit<3> configures forward fast swap. 0 = disable forward fast swap (default) 1 = enable forward fast swap <2> not used not used <1> disable woc fault bit<1> enables and disables woc fault. 0 = enable woc (default) 1 = disable woc <0> system side woc threshold bit<0> configures the system si de woc fault comparator value. 0 = 20mv (default) 1 = 30mv table 12. control2 register 0x3dh (continued) bit bit name description
fn8896 rev.2.00 page 30 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands table 13. control3 register 0x4ch bit bit name description <15> re-read prog pin resistor bit<15> re-read prog pin resistor or not before switching. 0 = re-read prog pin resistor (default) 1 = do not re-read prog pin resistor <14> not used <13> not used <12> reverse startup debounce time bit<12> configures startup debounce time for reverse mode. 0 = debounce time is 200us (default) 1 = debounce time is 10us <11> forward startup debounce time bit<11> configures startup debounce time for forward mode. 0 = debounce time is 200us (default) 1 = debounce time is 10us <10:8> force operating mode bit< 10:8> enables or disables force o perating mode. 0xx: no effect 100: no switching, do not use 101: buck mode 110: boost mode 111: buck-boost mode <7> not used <6> current loop feedback gain bit<6> configures current loo p feedback gain for high current. 0 = gain x 1 (default) 1 = gain x 0.5 <5> input current limit loop bit<5> disables input current limit loop. 0 = enable input current limit loop (default) 1 = disable input current limit loop <4> not used not used <3> disabled ref amplifier for use with external reference bit<5> disables ref amplifier. 0 = enable ref amplifier (default) 1 = disable ref amplifier <2> digital reset bit<2> resets a ll smbus register values to por default value and restarts switching. 0 = idle (default) 1 = reset <1> buck-boost switching period bit<1> configures s witching period in buck-boost mode. 0 = period x 1 (default) 1 = period x 2 (half switching frequency) <0> pgood setting bit<0> confi gures pggod assert condition. 0 = pgood suppressed until v ref equals to vdac (default) 1 = pgood assert when switching starts table 14. control4 register 0x4eh bit bit name description <15:8> not used 7 reverse mode current prochot# bit<7> enables or disables trigge r prochot# with current in rev erse mode. 0 = enable (default) 1 = disable 6 forward sleep mode bit<7> enable s or disables chip sleep mode i n forward mode regardless of adp voltage. rvsen pin or control1 bit <11 > can override this function. 0 = disable (default) 1 = enable <5:2> not used
fn8896 rev.2.00 page 31 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands 5.8 regulating voltage re gister in reverse mode the reverseregulatingvoltage reg ister contains smbus readable a nd writable reverse mo de output regulation voltage reference. the default v alue is 5.004v. this register a ccepts any voltage comma nd but only the valid register bits will be written to the register. however, the reg ister shouldnt be progr ammed higher than the recommended operating voltage. in reverse mode, the u ser also can configur e the regulating out put voltage on the adp side by setting the external voltage divider on the adp pin, without changing the reversereg ulatingvoltage register value. 1 prochot# clear bit<1> clears prochot#. 0 = idle (default) 1 = clear prochot# 0 prochot# latch bit<0> manually resets prochot#. 0 = prochot# signal auto-clear 1 = hold prochot# low once tripped table 15. reverseregulatingvoltage register 0x49h bit description <2:0> not used <3> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 12mv of regulating voltage in reverse mode. <4> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 24mv of regulating voltage in reverse mode. <5> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 48mv of regulating voltage in reverse mode. <6> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 96mv of regulating voltage in reverse mode. <7> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 192mv of regulating voltage in reverse mode. <8> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 384mv of regulating voltage in reverse mode. <9> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 768mv of regulating voltage in reverse mode. <10> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 1536mv of regulating voltage in reverse mode. <11> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 3072mv of regulating voltage in reverse mode. <12> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 6144mv of regulating voltage in reverse mode. <13> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 12288mv of regulating voltage in reverse mode. <14> 0 = add 0mv of regulating voltage in reverse mode. 1 = add 24576mv of regulating voltage in reverse mode. <15> not used maximum 27456mv table 14. control4 register 0x4eh (continued) bit bit name description
fn8896 rev.2.00 page 32 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands 5.9 output current limit register in reverse mode the reversecurrentlimit register contains smbus readable and wr itable reverse current limit. the default is 512ma. this register accepts any current command, but only the valid register bits will be written to the register. the maximum values are clamped at 4096ma for r s1 = 20m. 5.10 input voltage limit register the inputvoltagelimit register c ontains smbus readable and writ able input voltage limits. the default is 4.096v. this register accepts any command , but only the valid register bits will be written to the register. the maximum values are clamped at 18v. table 16. reversecurrentlimit register 0x4ah bit description <6:0> not used <7> 0 = add 0ma of output current limit in reverse mode. 1 = add 128ma of output current limit in reverse mode. <8> 0 = add 0ma of output current limit in reverse mode. 1 = add 256ma of output current limit in reverse mode. <9> 0 = add 0mv of output current limit in reverse mode. 1 = add 512ma of output current limit in reverse mode. <10> 0 = add 0mv of output current limit in reverse mode. 1 = add 1024ma of output current limit in reverse mode. <11> 0 = add 0mv of output current limit in reverse mode. 1 = add 2048ma of output current limit in reverse mode. <12> 0 = add 0mv of output current limit in reverse mode. 1 = add 4096ma of output current limit in reverse mode. <15:13> not used maximum 4096ma table 17. inputvoltagelimit register 0x4bh bit description <7:0> not used <8> 0 = add 0mv of input voltage limit. 1 = add 512mv of input voltage limit. <9> 0 = add 0ma of input voltage limit. 1 = add 1024mv of input voltage limit. <10> 0 = add 0mv of input voltage limit. 1 = add 2048mv of input voltage limit. <11> 0 = add 0mv of input voltage limit. 1 = add 4096mv of input voltage limit. <12> 0 = add 0mv of input voltage limit. 1 = add 8192mv of input voltage limit. <13> 0 = add 0mv of input voltage limit. 1 = add 16384mv of input voltage limit. <15:14> not used maximum 18000mv
fn8896 rev.2.00 page 33 of 48 nov 30, 2017 ISL95338 5. ISL95338 smbus commands 5.11 information register the information register contain s smbus readable information ab out manufacture and operating modes. tables 18 and 19 identify the bit locations o f the information available. table 18. information1 register 0x3ah bit description <3:0> not used <4> not used <6:5> not used <9:7> not used <10> not used <11> bit<11> indicates if syste msideprochot# is tripped or not. 0 = systemsideprochot# is not tripped 1 = systemsideprochot# is tripped <12> bit<12> indicates if adp sideprochot# is tripped or not. 0 = adpsideprochot# is not tripped 1 = adpsideprochot# is tripped <14:13> bit<14:13> indicate s the active control loop. 00 = voltage control loop is active 01 = system current loop is active 10 = adp current limit loop is active 11 = input voltage loop is active <15> bit<15> indicates if the inte rnal reference circuit is acti ve or not. bit<15> = 0 indica tes that ISL95338 is in low power mode. 0 = reference is not active 1 = reference is active table 19. information2 register 0x4dh bit description <4:0> program resister read out <7:5> bit<7:5> indicates the ISL95338 operation mode. 001: forward boost 010: forward buck 011: forward buck-boost 101: reverse boost 110: reverse buck 111: reverse buck-boost <11:8> bit<11:8> indicates the ISL95338 state machine status. 0000 = off 0010 = adp 0100 = vsys 0110 = enable reverse mode 1000 = enable ldo5 1110 = wait <12> not used <13> not used <14> bit<14> indicates forward switching enable. 0 = not enabled 1 = enabled <15> not used
fn8896 rev.2.00 page 34 of 48 nov 30, 2017 ISL95338 6. application information 6. application information 6.1 r3 modulator figure 24. r3 modulator figure 25. r3 modulator operation principles in steady state figure 26. r3 modulator operation principles in dynamic response figure 27. diode emulation comp r i l gm phase c r v w s q pwm l c o v o v cr + + + - - - comp pwm v cr hysteretic window vw pwm vcr vw comp ugate phase il lgate
fn8896 rev.2.00 page 35 of 48 nov 30, 2017 ISL95338 6. application information figure 28. period stretching the ISL95338 uses intersils pate nted robust ripple regulator ( r3) modulation scheme. the r3 modulator combines the best features of fi xed frequency pwm and hystereti c pwm, while eliminating many of their shortcomings. figure 24 on page 34 conceptually shows the r3 modulator circuit and figure 25 on page 34 shows the operation principl es in steady state. the fixed voltage window between vw and comp is called the vw w indow in the following discussion. the modulator charges th e ripple capacitor c r with a current source equal to g m (v in - v o ) during pwm on-time and discharges the ripple capacitor c r with a current source equal to g m v o during pwm off-time, where g m is a gain factor. the c r voltage v cr , therefore, emulates the induct or current waveform. the modula tor turns off the pwm pulse when v cr reaches vw and turns on the pw m pulse when it reaches comp. because the modulator works with v cr , which is a large amplitude a nd noise-free synthesized signal, it achieves lower phase jitter than a conventional hysteretic mode modulato r. figure 26 on page 34 shows the operation principles during dynamic response. the co mp voltage rises during dynamic response, turning on pw m pulses earlier and more freque ntly temporarily, whic h allows for higher control loop bandwidth than a conventional fixed frequency pwm modulator at the same steady-state switching frequency. the r3 modulator can operate in diode emulation (de) mode to in crease light-load effici ency. for example, in buck de mode the low-side mosfet conducts when the current is f lowing from source-to-drain and does not allow reverse current, emula ting a diode. as shown in figure 27 on page 34 , when lgate is on, the low-side mosfet carries current , creating negative voltage on the phase node due to the voltage drop across the on-resistance. the ic monitors t he current by monitoring the ph ase node voltage. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing the di rection and creating unnecessary power loss. similar operations apply for other mode s, such as boost and buck-boost mode. if the load current is light enough, as figure 27 shows, the inductor current wi ll reach and stay at zero before the next phase node pulse. at this stage, the regulator is in disco ntinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a and t he regulator will be in ccm, although the controller will be in de mode. figure 28 shows the operation principle in diode emulation mode at light load. the load gets incrementally lighter in the three cases from top to bottom. the pwm on-time is deter mined by the vw window size, therefore, it is the same, making the inductor curren t triangle the same in the thre e cases. the r3 modulato r clamps the ripple i l i l v cr i l v cr v cr vw ccm/dcm boundary light dcm deep dcm vw vw
fn8896 rev.2.00 page 36 of 48 nov 30, 2017 ISL95338 6. application information capacitor voltage v cr in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v cr , naturally stretchin g the switching period. the inductor curre nt triangles move further apart from each other, such that the inductor current average valu e is equal to the lo ad current. the reduced switching frequency helps increase light-load efficiency. 6.2 ISL95338 bidirectional bu ck-boost voltage regulator the ISL95338 bidirectional buck -boost voltage regulator drives an external n-channel mo sfet bridge comprised of two transistor pairs as shown in figure 2 . the first pair, q1 and q2, is a buck arrangemen t with the tra nsistor center tap connected t o an inductor input, as is the case wit h a buck converter in fo rward mode. the second transistor pair, q3 and q4, is a boost arrangement with the tra nsistor center tap connected to the same inductors output, as is the case with a boost converter in forward mode . this arrangement suppo rts the same operation mode in reverse direction. ? in forward buck mode, q1 and q2 turn on and off alternatively, while q3 remains off and q4 remains on. ? in forward boost mode, q3 and q4 turn on and off alternatively , while q1 remains on and q2 remains off. ? in forward buck-boost mode, q1 and q3 turn on at the same time , q3 turns off and q4 turns on, q1 turns off and q2 turns on, and after q2 and q4 turn off at the same time, and q1 and q3 turn on again. ? in forward bypass mode, q1 and q4 are always on, while q2 and q3 are always off. ? in reverse buck mode, q3 and q4 turn on and off alternatively, while q2 remains off and q1 remains on. ? in reverse boost mode, q1 and q2 turn on and off alternatively , while q4 remains on and q3 remains off. ? in reverse buck-boost mode, q4 and q2 turn on at the same time , q2 turns off and q1 turns on, q4 turns off and q3 turns on, and after q3 and q1 turn off at the same time and q4 and q2 turn on again. ? in reverse bypass mode, q1 and q 4 are always on, except during the needed refresh time, while q2 and q3 are always off. ? in reverse mode the output sensing point is csip pin. figure 29. buck-boost regulator topology table 20. operation mode mode q1 q2 q3 q4 forward buck control fet sync. fet off on forward boost on off control fet sync. fet forward buck-boost control fet sync. fet control fet sync. fet forward bypass on off off on reverse buck on off sync. fet control fet reverse boost sync. fet control fet off on reverse buck-boost sync. fet control fet sync. fet control fet reverse bypass on off off on &6,1 &621 &6,3 &623 4 4 4 4 9287 6<67(0 /2$' / 5 6 5 6 9$'3
fn8896 rev.2.00 page 37 of 48 nov 30, 2017 ISL95338 6. application information the ISL95338 optimizes the opera tion mode transition algorithm by considering the input and output voltage ratio and the load condition. when adp voltage v adp is rising and is higher than 94% of the system bus voltage vsy s, the ISL95338 will transit from boost mode to buck-boost mode. i f v adp is higher than 120% of vsys, the ISL95338 will transit from buck-b oost mode to buck mode under a ny circumstance. at a heavier load, the mode transition point changes accordin gly to accommodate the duty cy cle change due to the po wer loss on the voltage regulator circuit. when the adp voltage v adp is falling and is lower than 106% of the system bus voltage vs ys, the ISL95338 will transit from buck mode to buck-boost mode. if v adp is lower than 80% of vsys, the ISL95338 will transit from buck-boost mode to boost mode. figure 30. operation mode when the reverse function is ena bled with the smbus command or rvsen pin, and if reverse voltage vsys is higher than 4.1v, the ISL95338 operates in reverse mode. the customer can enable bypass m ode with control1 register bit 4 . when the bypass mode control bit is enabled, the ref will ramp to the input v oltage, and the switcher will c ontinue switching until the output voltage is in the 300mv window to the input. when the regulating voltage is withi n the 300mv window to the input voltage, the latch will be set to stop the sw itching, q1 and q4 will be alwa ys on while q2 and q3 will be always off, and uv and ov will be disabled. to exit bypass mode, unprogram control 1 register bit 4, then the ref will ramp to dac and the switching will resume. 6.3 soft-start the ISL95338 includes a low powe r ldo with nominal 5v output, w hich input is or-ed f rom the vout pin and adp pin. the ISL95338 also inclu des a high power ldo with nomin al 5v output, which input is from the dcin pin connected to the adp and the system bus, through an externa l or-ing diode circuit. both ldo outputs are tied to the vdd pin to provide the bias power and gate drive power f or ISL95338. the vddp pin is the ISL95338 gate drive power supply input. use an r-c filter to generate the vdd p pin voltage from the vdd pin voltage. when vdd > 2.7v, the ISL95338 digital block is activated. the s oft-start time can be set by the external capacitor on ref pin. the ISL95338 sources 1a current out of the ref pin to charge this external capacitor. its voltage will be used as the output voltage ref erence in the soft-start proce dure. 6.4 programming options the resistor from the prog pin to gnd programs the forward outp ut voltage configuratio n of the ISL95338. table 21 shows the programing options. 94% 120% 106% 80% vsys vadp vadp buck-boost buck boost boost buck-boost buck
fn8896 rev.2.00 page 38 of 48 nov 30, 2017 ISL95338 6. application information the switching frequency can be ch anged through smbus control1 r egister bit<9:7> after por. refer to smbus control1 register programming table for a detailed description. after por, the ISL95338 will source 10a current out of the pro g pin and read the prog pin voltage to determine the resistor value. if ISL95338 is powered up from reverse side , it will not read prog resistor. once frwen is enabled, ISL95338 will reset the forward regulating voltage reg ister to its default valu es according to the prog pin setting. by default, the adp cur rent-sensing resistor r s1 is 20m and vs ys current-sensing resistor r s2 is 10m. using these r s1 = 20m ? and r s2 = 10m options would result in 4ma/lsb correlation in the smbu s current commands. if r s1 and r s2 values are different from these r s1 = 20m ? and r s2 = 10m options, the smbus command needs to be scaled accordingly to obtain the correct current. smaller cu rrent-sense resistor val ues reduce the power loss whereas larger current-sense re sistor values give better accura cy. the illustration in this datasheet is based on current-sensing resistors r s1 = 20m and r s2 = 10m unless specified otherwise. 6.5 de operation in de mode of operation, the isl 95338 employs a phase comparato r to monitor the phase node voltage to the ground or vout or adp voltage dur ing the low-side switching fet on-time to detect the inductor current zero crossing, depending on the operat ion mode (buck, buck-boost and boost) and power delivery direction (forward or reverse direction), refer to t he table 22. the phase compara tor needs a minimum on-time of the low-side switching fet for it to recogni ze inductor current zero crossin g. if the low-side switching fet on-time is too short for the phase comparator to su ccessfully recognize the inductor zero crossing, the ISL95338 may lose diode emulation ability. to prevent such a scenario, t he ISL95338 emp loys a minimum low-side switching fet on-time. when the intended low-side switching fet on-time is shorter tha n the minimum value, the ISL95338 stretches the switching period to keep the low-side switching fet on-time at the minimum value, w hich causes the ccm switching frequency to d rop below the set point. table 21. prog pin programming options prog-gnd resistance (k) default forward regulating voltage min max 028 5.004 35.7 71.5 9.000 82.5 133 12.000 147 215 16.008 237 open 20.004 table 22. voltage comparator for de operation mode direction voltage comparator buck forward phase 1to gnd boost forward phase 1to vout buck-boost forward phase 1to vout buck reverse phase 2 to gnd boost reverse phase 1to adp buck-boost reverse phase 1to adp
fn8896 rev.2.00 page 39 of 48 nov 30, 2017 ISL95338 6. application information 6.6 forward mode when the forward function is enabled with the smbus command or frwen pin (voltage is higher than 0.8v) and dcin is powered by adp, and if the adp is plugged in and its va lue is higher than 4.1v, the ISL95338 can operate in forward buck mode, forward b oost mode, forward buck-boost mo de, or forward bypass mode. after the forward output voltage reaches the regulatin g output voltage ra nge set by register 0x15h bit<14:3>, forward power-good fwgpg will assert to high. 6.7 reverse mode for usb otg (on-the-go) when the reverse function is ena bled with the smbus command (co ntrol1 bit 11) or rvsen pin, and if an external voltage is on system si de and its value is higher than 4.1v, the ISL95338 can operate in reverse buck mode, reverse boost mode, reverse buck-boost mode, or reverse b ypass mode. rvsen is the digital input pin. the 1.3s or 150ms debounce time can be set by control2 register bit<13>. after the reverse output voltage reaches the output voltage set by register 0x49h bit<14:3>, reverse pow er-good rvspg will assert to high. before reverse mode starts sw itching, the csip pin voltage need s to drop below the reverse output overvoltage protection threshold (reverseregu latingvoltage + 1177mv) first. the default reverse output volta ge is 5v and programmable up to 20v in reverse buck, reverse buck-boost, and reverse boost mode. in reverse b ypass mode, the maximum value o f reverse output voltage is programmable up to 20v. the reverse voltage regis ter 0x49h can be used to confi gure the reverse output voltage. 6.8 fast ref to achieve fast ref in some applications, the fast ref function can be programmed by control1 bit3. if this bit is programmed, 1ua curren t source for ref pin will be replaced wit h 5k impedance to get fas ter transitions for ref voltage. 6.9 fast swap the ISL95338 provides fast swap function in forward mode and re verse mode. users can implement the fast swap function in forward mode in one o f two ways (pin reverse or sof tware reverse) by following the steps below: ? pin reverse fast swap enable: (1) program control2 bit4 (reverse fast swap). (2) skip trim during restart by programming control1 bit 13. (3) skip autozero during restart by programming control1 bit 12. (4) enable rvsen pin. ? software reverse fast swap enable: (1) program control1 bit0 (force 5.04v vdac). (2) program control1 bit3 (fast ref). (3) skip trim during restart wi th programming control1 bit 13. (4) skip autozero during restart wi th programming control1 bit 1 2. (5) program control1 bit11 (force reverse mode). similarly, users can implement t he fast swap function in revers e mode in one of two ways (pin reverse or software reverse) by following the steps below: ? pin forward fast swap enable: (1) program control2 bit3 (forward fast swap). (2) skip trim during restart by programming control1 bit 13. (3) skip autozero during restart by programming control1 bit 12. (4) disable rvsen pin. (5) enable fwren pin. ? software forward fast swap enable:
fn8896 rev.2.00 page 40 of 48 nov 30, 2017 ISL95338 6. application information (1) program control1 bit0 (force 5.04v vdac). (2) program control1 bit3 (fast ref). (3) skip trim during restart by programming control1 bit 13. (4) skip autozero during restart by programming control1 bit 12. (5) un-program control1 bi t11 (force reverse mode). 6.10 way overcurren t protection (wocp) the ISL95338 provides way overcu rrent protection (wocp) against the mosfet short, system side and adp side short, and inductor short scenarios. the ISL95338 monitors the csip-csin voltage and cson-csop voltage and compares them to the wocp threshold 12a for adp current and 20a for system side current in forward mode. when the woc comparator is tri pped, the ISL95338 counts one tim e within each 10s wi ndow. if the ISL95338 counts woc to 7 times in 50ms, it stops switching immediately. after the 1.3s or 150ms debounce time is set by control2 register bit<12>, the i sl95338 goes through the start- up sequence to retry. the wocp function can be disabl ed through control2 register bit <1>. 6.11 adp input overvoltage protection if the adp pin input voltage ex ceeds 26.4v for mor e than 10s, the ISL95338 wi ll declare an adp overvoltage condition and stop switching. when the adp voltage drops below 25.608v for more than 100s, the ISL95338 will start to switch. 6.12 system output ov ervoltage protection the ISL95338 provides system rail output overvoltage protection . if the system voltage vouts is 1095mv higher than the forwardregulatingvoltage register set value for more t han 100us, it will declare the system overvoltage, de-assert fwrpg, and stop switching. it will resume switching w ith the 100us debounce when vouts is less than 542mv plus the setting refer ence voltage fo r forward. 6.13 system output unde rvoltage protection the ISL95338 provides system ra il output undervoltage protectio n. if the system voltage vouts is 818mv lower than the forwardregulatingvoltage register set value for more t han 1ms, it will declare the system undervoltage, de-assert fwrpg, and restart. 6.14 adp output overvoltage protection the ISL95338 provides adp rail o utput overvoltage protection. i f the adp voltage adps is 1177mv higher than the reverseregulatingvoltage register set value for more than 1 00us, it will declare the adp overvoltage, de-assert rvspg, and stop switching. the is l95338 will resume switching w ith the 100us debounce when adps is less than 583mv plus the setting reference voltage for reverse. 6.15 adp output underv oltage protection the ISL95338 provides adp rail out put undervoltage protection. if the adp voltage v adps is 1177mv lower than the reverseregulatingvoltage register set value for more t han 1ms, it will declare the adp undervoltage, de- assert rvspg, and stop switching. 6.16 over-temperature protection the ISL95338 will stop switching for self protection when the j unction temperature exceeds +140c. when the temperature falls below +120c, and after a 100s dela y, the ISL95338 will start switching.
fn8896 rev.2.00 page 41 of 48 nov 30, 2017 ISL95338 6. application information 6.17 switching power mosfet gate capacitance the ISL95338 includes an internal 5v ldo output at the vdd pin, which can be used to provide the switching mosfet gate driver power through the vddp pin with an r-c filte r. the 5v ldo output overcurrent protection threshold is 115ma nominal. when selecting the switching power mosfet, the mosfet gate capacitance should be considered carefully to avoi d overloading the 5v ldo, especi ally in buck-boost mod e when four mosfets are switching at the same time. for one mosfet, the gate drive current can be estimated by equation 1 : where: ?q g is the total gate adp which can be found in the mosfet datashe et ?f sw is switching frequency 6.18 adp side input filter the adp cable parasitic inductance and capacitance could cause some voltage ringing or an overshoot spike at the adp connector node when the adp is hot plugged in. this voltage spike could damage the ISL95338 pins connecting to the adp connector node. one low cost solution is to add an rc snubber circuit at the adp connector node to clamp the voltage spike as shown in figure 31 . a practical value of the rc snubber is 2.2 to 2.2f; however, the appropriate values and power rating should be care fully characterized based on the actual design. additionally, it is not recommende d to add a pur e capacitor at the adp connector node, wh ich can cause an even bigger voltage spike due to the adp cable or the adp current pa th parasitic inductance. figure 31. adapter input rc snubber circuit i driver q g f ? sw = (eq. 1) ISL95338 acin adapter connector r i c i 2.2 2.2f rc snubber
fn8896 rev.2.00 page 42 of 48 nov 30, 2017 ISL95338 7. general application information 7. general application information this design guide is intended to provide a high-level explanati on of the steps necessary t o design a single-phase power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following section. in additio n to this guide, intersil prov ides complete reference designs that include schematics, bill of materials , and example board layouts. 7.1 select the lc output filter the duty cycle of an ideal buc k converter in ccm is a function of the input and the output voltage. this relationship is written by equation 2 : the output inductor p eak-to-peak ripple cu rrent is written by equation 3 : a typical step-down dc/dc converter will have an i p-p of 20% to 40% of the maximum dc output load current for a practical design. the value of i p-p is selected based upon several c riteria such as mosfet switchi ng loss, inductor core loss, and the res istive loss of the inductor wind ing. the dc copper loss of the i nductor can be estimated by equation 4 : where i load is the converter output dc current. the copper loss can be significan t so attention has to be given to the dcr selection. ano ther factor t o consider when choosing the inductor is its saturation characteristics at elevated temperatures. a saturated inductor could cause destruction of circuit components. a dc/dc buck regulator mus t have output capacitance c o , into which ripple current i p-p can flow. current i p-p develops a corresponding ripple voltage v p-p across c o, which is the sum of the volta ge drop across the capacitor esr and of the voltage change ste mming from adp moved in and ou t of the capacitor. the se two voltages are written by equations 5 and 6 : if the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the to tal esr until the required v p-p is achieved. the inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high s lew rate. low inductance capacitors should be considered in this scenario. a c apacitor dissipates heat as a f unction of rms current and frequency. be sure that i p-p is shared by a sufficient quan tity of paralleled capacitors so that they operate below the maximum rated rms current at f sw . take into account that the rat ed value of a capacitor can fad e as much as 50% a s the dc voltage across it increases. d v out v in --------------- = (eq. 2) (eq. 3) i p-p v out 1d C ?? ? f sw l ? ------------------------------------- - = (eq. 4) p copper i load 2 dcr ? = ? v esr i p-p e ? sr = (eq. 5) ? v c i p-p 8c o f ? sw ? ----------------------------- = (eq. 6)
fn8896 rev.2.00 page 43 of 48 nov 30, 2017 ISL95338 7. general application information 7.2 select the input capacitor the important parameters for the input capacitan ce are the volt age rating and the rms curre nt rating. f or reliable operation, select cap acitors with voltage and current ratings a bove the maximum input voltage and capable of supplying the rms current required by the switching circuit. th eir voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a preferred rating. the typical application circuit on page 2 is a graph of the input capacito r rms ripple current, normaliz ed relative to output load current, as a function of d uty cycle and is adjusted for c onverter efficiency. th e normalized rms ripple current calculation is written as equation 7 : where: ?i max is the maximum continuous i load of the converter ? k is a multiplier (0 to 1) corr esponding to the inductor peak- to-peak ripple amplitude expressed as a ratio of i max (0 to 1) ? d is the duty cycle that is ad justed to take into account the efficiency of the convert er, which is written as equation 8 : in addition to the capacitance, s ome low esl ceramic capacitanc e is recommended to decoup le between the drain of the high-side mosfet and the source of the low-side mosfet. figure 32. normalized rms input current at eff = 1 (eq. 7) i c in rms normalized , ?? i max d1d C ?? ? dk 2 ? 12 -------------- + ? i max --------------------------------------------------------------- -------- = d v out v in eff ? -------------------------- = (eq. 8) normalized input rms ripple current duty cycle 00.1 0.2 0.3 0.4 0.6 0.7 0.8 0.9 1.0 0.5 0 0.12 0.24 0.36 0.48 0.60 k = 0.75 k = 0.5 k = 0.25 k = 0 v s = 2.5v k = 1
fn8896 rev.2.00 page 44 of 48 nov 30, 2017 ISL95338 7. general application information 7.3 select the switc hing power mosfet typically, a mosfet cannot tolerat e even brief excursions beyon d their maximum drain-to-source voltage rating. the mosfets used in the power stage of the converter should hav e a maximum vds rating that exceeds the sum of the upper voltage tolerance of the inp ut power source and th e voltage spike that occurs when the mosfet switches off. several power mosfets are readily available that are optimized for dc/dc converter appl ications. the preferred high-side mosfet emphasizes low g ate adp so that the device spe nds the least amount of time dissipating power in the linear region. unlike the low-side mosfet, which has the drain-to-source voltage clamped by its body diode during turn off, the high-side mosfet turns off with a vd s of approximately v in - v out , plus the spike across it. the preferred low- side mosfet emphasizes low r ds(on) when fully saturated t o minimize conduction loss. it should be noted that thi s is an optimal configuration of mosfet selection for lo w duty cycle applications (d < 50%). for higher output, lo w input voltage solutions, a mo re balanced mosfet sel ection for high- and low-side devices may be warranted. for the low-side (ls) mosfet, the power loss can be assumed to be conductive only and is written as equation 9 : for the high-side (hs) mosfet, the conduction loss is written a s equation 10 : for the high-side mo sfet, the switching loss is written as equation 11 : where: ?i valley is the difference of the dc comp onent of the inductor current minus 1/2 of the inductor ripple current ?i peak is the sum of the dc component of the inductor current plus 1/ 2 of the inductor ripple current ?t sw(on) is the time required to drive the device into saturation ?t sw(off) is the time required to dr ive the device into cut-off 7.4 select the bootstrap capacitor the selection of the bootstrap capacitor is written by equation 12 : where: ?q g is the total gate adp required to turn on the high-side mosfet ? ? v boot is the maximum allo wed voltage decay across the boot capacitor each time the high-side mosfet is switched on as an example, suppose the high- side mosfet has a total gate ad p q g of 25nc at v gs = 5v and a ? v boot of 200mv. the calculated bootstrap capacitance is 0.125f; for a c omfortable margin, select a capacitor that is double the calculated capacitance. in this example, 0.22f will suffic e. use an x7r or x5r ceramic capacitor. (eq. 9) p con_ls i load 2 r ? ds on ?? _ls 1d C ?? ? ? ? ? p con_hs i load 2 r ? ds on ?? _hs d ? = (eq. 11) p sw_hs v in i valley t sw on ?? f ? sw ? ? 2 --------------------------------------------------------------- --------------- v in i peak t sw off ?? f ? sw ? ? 2 --------------------------------------------------------------- ----------- - + = c boot q g ? v boot ----------------------- - = (eq. 12)
fn8896 rev.2.00 page 45 of 48 nov 30, 2017 ISL95338 7. general application information 7.5 select the resistor div ider for vouts and adps figure 33. resistor divi der for vouts and adps adps and vouts are output voltage feedback pins, i n reverse mod e and forward mode, respectively, which allow the customer to change output voltage by the resistor div ider (r 1 , r 2 , and r 3 , r 4 ), as shown in figure 2 . there are two parallel resistors (1m and 1.5m) inside from vout s and adps to ground. for example, in forward mode, vsys voltage magnitude can be revised by tuning r 1 and r 2 values, written by equation 13 . thus, there is no need to change the forward reg ulating voltage register (0x15 h) through gui. the same process can be applied at the adps pin. 1m 1m 1.5m 1.5m vouts adps vsys vadp ISL95338 r 1 r 2 r 3 r 4 v outs v sys 1.5m\\1m\\r 2 ?? 1.5m\\1m\\r 2 ?? r 1 + -------------------------------------------------------- - = (eq. 13)
fn8896 rev.2.00 page 46 of 48 nov 30, 2017 ISL95338 8. revision history 8. revision history rev. date description 2.00 nov 30, 2017 added way overcurrent protection (wocp) functio n to datasheet. 1.00 oct 5, 2017 removed way overcurrent protection (wocp) functi on 0.00 aug 15, 2017 initial release
fn8896 rev.2.00 page 47 of 48 nov 30, 2017 ISL95338 9. package outline drawing 9. package outline drawing l32.4x4a 32 lead quad flat no-lead plastic package rev 5, 2/16 bottom view detail x side view typical recommended land pattern top view located within the zone indicated . the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.25mm from the terminal tip. dimension applies to the metal lized terminal a nd is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: pin #1 6 b 0.10 ma c 32x 0.20 24x 0.40 2.65 8x 0.179 8x 0.179 8x 0.36 28x 0.40 index area pin 1 6 a b (4x) 0.15 c seating plane base plane 0.08 see detail x c c 0.10 // 0.90 0.10 0.00 min 0.05 max 5 0.2 ref (32x 0.60) (32x 0.20) (28x 0.40) (2.80) (3.80) (3.80) (2.65) 2.80 c 4 index area 4.00 0.05 4.00 0.05 for the most recent package outline drawing, see l32.4x4a .
fn8896 rev.2.00 page 48 of 48 nov 30, 2017 ISL95338 10. about intersil intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordi ngly, the reader is cautioned to verify that datasheets are current befo re placing orders. information furnished by intersil is beli eved to be accurate and r eliable. however, no responsibility is assumed by intersil or its subsidiaries for it s use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent righ ts of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. 10. about intersil intersil corporation is a leadi ng provider of innovative power management and precision analog solutions. the company's products address some of the largest markets within t he industrial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related documentation, an d related parts, see th e respective product information page found at www.intersil.com . for a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary . you can report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support .

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